Reliable Chip Designs from Low-Powered Unreliable Components


25th November, 14:30-15:30

The on-going miniaturization of data processing and storage devices and the low-energy consumption imperative can only be sustained through low-powered components. However, lower supply voltages combined with the intrinsic device variations introduced by emerging nanoelectronic device fabrication process make them inherently unreliable. As a consequence, the nanoscale integration of reliable chips built out of unreliable components emerged as one of the most critical challenges for the next-generation electronic circuit design. In this talk we present the main ideas of a foundational breakthrough towards reliable, fault-tolerant chip design from unreliable components. Our strategy builds upon the observation that while error correcting codes proved to be a fundamental information theory cornerstone, enabling efficient reliable communication over unreliable channels, their capabilities were not really utilised in hardware design methods. The main idea behind our approach is to acquire error-free computing with error-prone components by detouring error correcting codes from their traditional use, such that they can provide efficient protection against circuit-level induced errors. In this line of reasoning we rely on the synergistic utilisation of (1) information theory and coding techniques, traditionally utilised to improve the communication systems reliability and (2) circuit and system theory and design techniques, in order to create reliable/ predictable hardware platforms. 

Sorin Coțofană

Delft University

Sorin Cotofana received the M.Sc. degree in Computer Science from the "Politechnica" University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently an Associate Professor with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focused on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 300 papers in peer-reviewed international journal and conferences, and received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015), and IEEE Nano Council CASS representative (2013-2014), and has been actively involved in the organization of many international conferences. He is currently Associate Editor in Chief and Senior Editor for IEEE Transactions on Nanotechnology and Steering Committee member for IEEE Transactions on Multi-Scale Computing Systems. He is a HiPEAC member and a senior IEEE member (Circuits and System Society (CASS) and Computer Society).